D&T Special Issue - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information

Scope

A great challenge for future information technologies is building reliable systems on top of unreliable components. Parameters of modern and future technology devices are affected by severe levels of process variability and devices will degrade and may even fail during the normal lifetime of a system due to aging. These extreme levels of variability are caused by the high device miniaturization and the random placement of individual atoms. Variability is considered a “red brick” by the International Technology Roadmap for Semiconductors.

Devising new approaches so that future integrated circuits (especially memories and microprocessors) are resilient to variability and lifetime degradation in a transparent manner for the users is key for future systems. The design and test of computers are facing unique challenges related with this ambitious target on variability and reliability, which affects all levels of the design hierarchy, from the technology level to the circuit and architecture/system level.

IEEE Design and Test seeks original manuscripts for a special issue on the “Variability and Aging” topic, scheduled for publication in November/December 2013. This special issue will cover recent works on variability and aging, including modeling circuit techniques, and innovative monitoring and countermeasure mechanisms at the circuit, micro-architectural and system level to mitigate variability and improve reliability.

Paper submissions are encouraged for bulk CMOS and bulk and SOI FinFET devices but also for other emerging technologies that may be used for the design of future memories and processors.

Topics of interest include (but are not limited to)

Analysis of the mechanisms of variability and aging in modern technologies, compact models.
Analysis of the impact on memory (SRAM, DRAM and non-volatile memories) and processor systems.
Design of variability and aging compensating techniques and countermeasures at circuit level for both memories and processors.
Development of methodologies for specifying and implementing performance-, power- and reliability –aware adaptive reconfiguration policies of systems.

Submissions

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Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at https://mc.manuscriptcentral.com/cs-ieee. Indicate that you are submitting your article to the special issue on ‘‘Variability and Aging’’. All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 200 words) and a maximum of 12 References (50 for surveys). This amounts to about 4,000 words of text and a maximum of five small to medium figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, passive to active voice, logical organization, readability, and adherence to style. Please see IEEE D&T Author Resources at http://www.computer.org/dt/author.htm, then scroll down and click on Author Center for submission guidelines and requirements.

Key Dates

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Articles due for review: 1st February 2013
Reviews completed: 15th April 2013
Articles revisions due: 1st May 2013
Notice of final acceptance: 1st June 2013
All material due to edit: 15th July 2013 (hard deadline)
Publication date: November/December 2013

Additional Information

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Please direct questions regarding this special issue to Guest Editors:

Antonio Rubio (antonio.rubio@upc.edu)
Antonio Gonzalez (antonio.gonzalez@intel.com)

For more information, visit us on the web at: https://mc.manuscriptcentral.com/cs-ieee